18. Jun 2010
Integrated Design, Verification and Reuse for FPGA design flows
WEDASoft Software and Technology Park Ljubljana are inviting you to attend an international seminar on Mentor Graphics' design flow for FPGA (and ASIC) designers, which will take place on 7 July at Technology Park Ljubljana.
Aim of the seminar is to present the enabling technologies that Mentor provides to enable companies and research establishments to more rapidly and effectively create and verify designs which incorporate a mix of new and existing RTL.
Assessing the quality of RTL code can be a subjective matter
Requirements Tracking
By automating tracking implementation can be qualified by the design coding, the test bench coding and the test bench coverage.
Using Assertion Monitors for automatic functional checks
Assertions allow both designer engineers and verification engineers to concisely describe the intended and required functionality of RTL code.
Who Should Attend
Registration is obligatory and should be sent to Kaja Rangus by e-mail: kaja.rangus@tp-lj.si.
Deadline for submitting the application form is 5th June 2010.
Number of participants is strictly limited. Participation is free of charge.
The Lecturer: Neil Rattray
Neil Rattray holds a B.Eng in Electronic Engineering from Queen Mary College, University of London, and has over 20 years experience in ASIC and FPGA design. He worked initially for 8 years for several defence companies in the UK. From there, he went into applications engineering for first Actel and then Xilinx distributors where he supported many customers across the UK and Ireland. He then worked for 7 years for Saros Technology supporting numerous EDA vendors, including Mentor. For the past 18 months Neil has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects across Europe.
About WEDASoft
WEDASoft Software GesmbH. is Austria's leading distributor for electronic design application tools for many years. The private family owned company was founded 1993 under the name of SELB OEG and renamed 2000 to WEDASoft. In the meanwhile WEDASoft looks after the countries Slovenia, Croatia, Bosnia and Herzegovina as well as Hungary next to the home market, too. In these countries WEDASoft is responsible for the sales of electronic hardware and software design solutions of Mentor Graphics®, Downstream, JTAG Boundary Scan and others.
Furthermore WEDASoft is a recognized and competent service and support center for PCB design and Boundary scan. Our leading product portfolio and our professional competence in solution providing united with the power of esteem toward our customers make us a respected partner for industry and research.
Since the beginning the company is leaded by the founder – Ing. Ernst Wurzer. And since then the satisfaction of the customers as well as the welfare of the employees is the driving force of WEDASoft’s daily work.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide.
Mentor Graphics® provides software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. Mentor Graphics® offers innovative
products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design.
Aim of the seminar is to present the enabling technologies that Mentor provides to enable companies and research establishments to more rapidly and effectively create and verify designs which incorporate a mix of new and existing RTL.
Seminar will cover the following key areas
Accelerating RTL Reuse
RTL capture and visualization capabilities of the Mentor Graphics FPGA Design flow
Assessing the quality of RTL code can be a subjective matter
Requirements Tracking
By automating tracking implementation can be qualified by the design coding, the test bench coding and the test bench coverage.
Using Assertion Monitors for automatic functional checks
Assertions allow both designer engineers and verification engineers to concisely describe the intended and required functionality of RTL code.
Who Should Attend
- FPGA/ASIC Design Engineers
- Verification Engineers
- Project Managers
- Educational Researchers / Research post-graduates
Registration is obligatory and should be sent to Kaja Rangus by e-mail: kaja.rangus@tp-lj.si.
Deadline for submitting the application form is 5th June 2010.
Number of participants is strictly limited. Participation is free of charge.
The Lecturer: Neil Rattray
Neil Rattray holds a B.Eng in Electronic Engineering from Queen Mary College, University of London, and has over 20 years experience in ASIC and FPGA design. He worked initially for 8 years for several defence companies in the UK. From there, he went into applications engineering for first Actel and then Xilinx distributors where he supported many customers across the UK and Ireland. He then worked for 7 years for Saros Technology supporting numerous EDA vendors, including Mentor. For the past 18 months Neil has worked as an Application Engineer supporting Mentor's line of Functional Verification Projects across Europe.About WEDASoft
WEDASoft Software GesmbH. is Austria's leading distributor for electronic design application tools for many years. The private family owned company was founded 1993 under the name of SELB OEG and renamed 2000 to WEDASoft. In the meanwhile WEDASoft looks after the countries Slovenia, Croatia, Bosnia and Herzegovina as well as Hungary next to the home market, too. In these countries WEDASoft is responsible for the sales of electronic hardware and software design solutions of Mentor Graphics®, Downstream, JTAG Boundary Scan and others.
Furthermore WEDASoft is a recognized and competent service and support center for PCB design and Boundary scan. Our leading product portfolio and our professional competence in solution providing united with the power of esteem toward our customers make us a respected partner for industry and research.
Since the beginning the company is leaded by the founder – Ing. Ernst Wurzer. And since then the satisfaction of the customers as well as the welfare of the employees is the driving force of WEDASoft’s daily work.
About Mentor Graphics
Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies. Established in 1981, the company reported revenues over the last 12 months of about $800 million and employs approximately 4,425 people worldwide.
Mentor Graphics® provides software and hardware design solutions that enable companies to develop better electronic products faster and more cost-effectively. Mentor Graphics® offers innovative
products and solutions that help engineers overcome the design challenges they face in the increasingly complex worlds of board and chip design.
